A Parallel Architecture for Video Compression

Authors:
S. Bhattacharjee;S. Das;D. Saha;D. Roychowdhury;P. Pal Chaudhuri
Affiliations:
-;-;-;-;-
Venue:
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
Year:
1997

Citing 3
Cited 2

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Implementing a WLAN video terminal using UML and fully automated design flow

EURASIP Journal on Embedded Systems

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Abstract

This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352/spl times/272 pixels.