Connected components in binary images: the detection problem
Connected components in binary images: the detection problem
Connected component labeling of binary images on a mesh connected massively parallel processor
Computer Vision, Graphics, and Image Processing
An EREW PRAM Algorithm for Image Component Labeling
IEEE Transactions on Pattern Analysis and Machine Intelligence
A systolic approach for real time connected component labeling
Computer Vision and Image Understanding
Sequential Operations in Digital Picture Processing
Journal of the ACM (JACM)
A Systolic Image Difference Algorithm for RLE-Compressed Images
IEEE Transactions on Parallel and Distributed Systems
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Connected component detection and labeling is an essential step in many image analysis techniques. In this paper, we propose a systolic VLSI architecture for labeling connected components in an image. The architecture has been designed and verified using Cadence Verilog-XL and also implemented on a rapid prototyping system using FPGA' s connected as a linear systolic array. Although, the algorithm has a time complexity of O(p), this is in terms of the actual clock cycle which is 15 ns. The proposed hardware can process a 128X128 image in 0.992 ms and uses 128 processors whereas the MPP requires 94.6 ms with 16384 processors.