Optimizing FPGA-Based Vector Product Designs
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Journal of Systems Architecture: the EUROMICRO Journal
Hi-index | 0.00 |
In this paper we present techniques for improving area efficiency of FIR filters implemented using the Distributed Arithmetic(DA) approach. These techniques exploit the flexibility in partitioning the filter coefficients for a two lookup-table (LUT) based DA implementation.The first technique is targeted at a ROM based implementation of LUTs and aims at minimizing number of columns/outputs of the ROMs. The second technique is targeted at a Hardwired implementation of LUTs. We have developed an estimation technique for relative area comparisons of Hardwired LUTs having the same number of inputs and outputs. We present a heuristic approach, based on this estimation technique, to optimally partition coefficients so as to achieve area-efficient Hardwired implementation of LUTs. We present results to show these techniques can result in 10\% to 15\% area reduction for ROM based implementations and 20\% to 25\% area reduction for Hardwired implementations.