Framework for Synthesis of Virtual Pipelines

Authors:
Srinivasan Dasasathyan;Rajesh Radhakrishnan;Ranga Vemuri
Affiliations:
Department of ECECS, ML0030, University of Cincinnati, Cincinnati, OH;Department of ECECS, ML0030, University of Cincinnati, Cincinnati, OH;Department of ECECS, ML0030, University of Cincinnati, Cincinnati, OH
Venue:
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Year:
2002

Citing 4
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Abstract

Virtual Pipelining allows designs of arbitrary size to execute on finite sized FPGA devices. It allows pipelined designs to be efficiently configured on a FPGA by overlapping the reconfiguration time of a pipeline stage with the execution time of previous pipeline stages. This technique produces performance improvement up to an order of 5 versus a non-pipelined execution of a design. We extend this principle for handling large designs that were previously too large to fit on an FPGA. This paper presents a framework for automatically synthesizing virtual pipelines on an Virtex FPGA. We also suggest criteria for extending our approach to non-Virtex FPGAs.