Power exploration for embedded VLIW architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Reducing dynamic and leakage energy in VLIW architectures
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, the main focus is on the interaction of power optimizing code transformations with the special performance improving sub-word instructions present in modern VLIW multi-media processors. The code transformations proposed by us heavily reduce the power consumption by moving the main part of the memory accesses from larger (off-chip) memories to smaller (on-chip) storage. In addition, most of the time their application also leads to system performance enhancement (in number of cycles) as well. Experimental results on real-life data-dominated applications clearly demonstrate that the application of our power optimizing code transformations approach is orthogonal to the use of instructions related to arithmetic (sub-word) parallelism exploitation. A second conclusion is that the positive impact of our transformations on performance is typically even larger than the effect of the sub-word instructions for the complete application.