A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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In this paper we propose a new model for short circuit power estimation of CMOS gates. The short circuit power of a CMOS gate is estimated by converting the gate into an equivalent CMOS inverter and all input signal waveforms into a single equivalent input signal for the inverter. The channel width and the input to the equivalent inverter are functions of the waveforms of all the inputs. This is different from the traditional approaches where only worst case situations are considered. HSPICE simulation of NAND gates using a commercial 0.25 micron CMOS process show that the proposed new short circuit power model for CMOS gates is much more accurate than previously reported models.