Representation of logic functions by if-then clauses

  • Authors:
  • P. K. Chiu

  • Affiliations:
  • Department of Electronic Engineering, Hong Kong Polytechnic

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 1989

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this short paper, an alternative representation of logic functions is proposed. Instead of using Boolean expressions to represent logic functions, a set of if-then clauses is used. It is shown how a Boolean expression can be translated to the equivalent form in general. This representation of logic functions speeds up the logic simulation and solves the deadlock problem in logic simulation using concurrent processes such as OCCAM.