A memory controller executing segment operations in time 0(1)

  • Authors:
  • H. Seebauer

  • Affiliations:
  • Institut für Informatik der Universität Bonn, Abteilung für Informatik IV, Römerstr. 164, 5300 Bonn 1, Federal Republic of Germany

  • Venue:
  • ACM SIGARCH Computer Architecture News
  • Year:
  • 1989

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Abstract

A memory controller unit is presented for segmentation of page structured memories. It is intended for the BARDE dataflow processor. Suitably programmed controllers used in parallel can handle arbitrary memory sizes. Segment allocation, release, and access (i.e. translation of a segment relative page addresses into a physical page address) are carried out in at most one add cycle. The allocation method described avoids storage fragmentation and garbage collection by numbering allocated and free pages. A memory controller consists of one page controller for each memory page. The translation from virtual into physical addresses is done by associative search amoag all page controllers.