An embedded real-time SIMD processor array for image processing

  • Authors:

  • D. Andrews;C. Kancler;B. Wealand

  • Affiliations:

  • -;-;-

  • Venue:
  • WPDRTS '96 Proceedings of the 4th International Workshop on Parallel and Distributed Real-Time Systems
  • Year:
  • 1996

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Abstract

The paper presents an overview of the SuperSPAR (Systolic Processor Array) architecture and chip set. The SuperSPAR was designed by Lockheed Martin to bring the benefits of massively parallel SIMD processing to the embedded systems domain. The system philosophy focused on building a hierarchy of scaleable subarray modules allowing systems to be configured by "plugging together" any number of these modules to meet specific system requirements. A typical SPAR system consists of three primary components: 1) a scalar processor board containing a scalar processor, local RAM, program ROM, a host I/O interface, and an Sbus interface, 2) a SPAR controller board which contains the SPAR's instruction and global memory, a transformer/splitter, an instruction queue, and a microcode sequencer, and 3) a SPAR array board which contains some number of interconnected SuperSPAR chips and their associated off-chip local data memories.