Performance enhancement of Banyan switch architecture under self-similar traffic

  • Authors:
  • J. Raja;S. Shanmugavel

  • Affiliations:
  • Department of ECE, S.R.M. Engineering College, Kattankulathur - 603 203. INDIA;Telematics Laboratory, School of ECE, Anna University, Chennai - 600 025. INDIA

  • Venue:
  • ICCC '02 Proceedings of the 15th international conference on Computer communication
  • Year:
  • 2002

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Abstract

The advancement in the field of computer technology, communication and the increasing user's demand in terms of bandwidth and speed, the future communication network is rolling towards the BISDN with optical technology. Asynchronous Transfer Mode(ATM) is one of the major transport mechanism, used to implement BISDN. In turn, the efficiency of the ATM network relies on the switching fabric. Hence, the switching fabric of future telecommunication systems should have a very low cell loss and delay performance. In this paper, the simulation results of the Sort Banyan architecture of size 8 × 8 are presented. The simulation of Sort Banyan network is performed for four different schemes to enhance the throughput. The cell loss versus the Hurst parameter for the four schemes viz., Input buffer, Inter-stage buffer, Shared output buffer and Regeneration of cells using FEC method are presented for Self-similar traffic models