Dynamic thermal management for MPEG-2 decoding
Proceedings of the 2006 international symposium on Low power electronics and design
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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In this paper, we propose the optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made timing/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for hardware implementation of the IDCT and VLD algorithms. Remaining parts were realized in software with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in high-level Verilog/VHDL hardware description language and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.