Efficient and Deterministic Parallel Placement for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper introduces the concept of "parallel genetic algorithms", to provide a solution for the placement problem for field programmable gate arrays, that complements routing to enhance the performance of the circuit implemented by the field programmable gate array. We propose to utilize the concept of parallelism to genetic algorithms to transform a set of initial populations of random placements to a final set of populations that contain solutions approximating the optimal one. The fundamental concept of this paper lies in sharing the good solutions among different processes, which may help the genetic algorithm to evolve its population in a more lucrative manner. In conjunction with the migration phase, we employ various genetic operators and the chosen fitness function, to expedite the transformation of the initial population towards the optimal solution. We have simulated the suggested method on a 64-node SGI Origin-2000 platform and the results are extremely encouraging, even for circuits with very large number of nets.