Computation of Two Texture Features in Hardware

Authors:
Katriina Heikkinen;Petri Vuorimaa
Affiliations:
-;-
Venue:
ICIAP '99 Proceedings of the 10th International Conference on Image Analysis and Processing
Year:
1999

Citing 0
Cited 3

FPGA architecture for fast parallel computation of co-occurrence matrices

Microprocessors & Microsystems
FPGA-based System for Real-Time Video Texture Analysis

Journal of Signal Processing Systems
Dedicated hardware for real-time computation of second-order statistical features for high resolution images

ACIVS'06 Proceedings of the 8th international conference on Advanced Concepts For Intelligent Vision Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents the hardware architectures of two texture features: mean and contrast. These features are based on the co-occurrence matrix method. However, the features can be calculated without the co-occurrence matrix, too. The formalism behind the features without the co-occurrence matrix is shown, and the corresponding hardware architectures are depicted with Data Flow Graphs (DFG). The architecture was developed with Very high speed integrated circuit Hardware Description Language (VHDL) and commercially available logic synthesis tool by Synopsis. The VHDL code was synthesized to Xilinx XC4000-series FPGA library.