Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the overall project needs and recommended project practices for a high-speed ATE interface. The interface between the device under test (DUT) and the test system is typically referred to as a DUT board or loadboard (herein referred to by Loadboard). The goal of developing a high-speed loadboard is to maintain high signal integrity on those signal lines where it is critical to the performance of the device, and accurate testing. This paper will focus more on project management, and fabrication issues in implementing a high-speed design and less on high-speed design techniques. High-speed design techniques will be touched upon as needed to illustrate the key message. The goal of this paper is to complement other design techniques based papers and provide a complete picture of a Loadboard activity.