Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The purpose of this paper is to explore the causes of measurement error relating to the device interface board (DIB or DUT (Device Under Test) board) in both ATE and bench characterization for devices operating over 1 Gigabit. Nearly all test setups for high-speed devices have the same basic features and characteristics. These characteristics combine to degrade both input and output signals (the data eye), especially at very high speeds. Within limits, the degradation is predictable. Therefore, DIB-induced errors can be improved and compensated.