Test sequence generation for controller verification and test with high coverage
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Verification is a critical phase in the development of any hardware and software system. Finite state machines have been widely used to model hardware and software systems. Therefore, testing finite state machines (FSMs) is an important issue. Coverage analysis of a test suite for a system's implementation determines the adequacy and the confidence level of the verification phase. In this paper, we derive a fault coverage metric for a test suite for an FSM specification. We also extend this metric for fault coverage estimation of interconnected FSMs. Finally, we propose symbolic input based fault coverage for large FSMs. In this paper, we also study incremental construction of a test suite associated with a coverage for a givenFSM specification.