Phase Locked Loop Using Delay Compensation Techniques

• Authors: Fulvio Spagna
• Venue: ISCC '00 Proceedings of the Fifth IEEE Symposium on Computers and Communications (ISCC 2000)
• Year: 2000

This paper illustrates a modification to a basic Phase Locked Loop (PLL) topology aimed at compensating the effects of loop latency. The technique, developed to address the performance degradation observed in high latency PLL topologies as is the case of Viterbi based decision directed Read Channel timing recovery, is readily applicable to digital baseband communication receivers.