Congestion control and traffic management in ATM networks: recent advances and a survey
Computer Networks and ISDN Systems
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
On the performance of early packet discard
IEEE Journal on Selected Areas in Communications
Credit-based flow control for ATM networks
IEEE Network: The Magazine of Global Internetworking
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The scalability of SDH/SONET to high speeds places strict performance requirements on ATM systems. Throughput preservation of link speed through protocols to a higher layer application is a known problem in high-speed communication systems, which becomes more acute as link speed increases and is being addressed with designs that offer high speed data paths and high embedded processing power.We introduce a specialized, high-speed, scalable and re-usable Queue Manager (QM) for ATM systems, which enables high-speed data transfer to/from system memory and management of logical data structures. We describe its architecture, and then we present implementations in hardware as well as in software for embedded systems. We evaluate the implementations, demonstrating the performance improvement and the system scalability.