Allocation and Data Arrival Design of Hard Real-time Systems

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  • Venue:
  • ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
  • Year:
  • 1997

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Abstract

This paper presents new models for process activation and process scheduling for real-time embedded systems. We introduce a realistic, yet high-level input data arrival model which includes both polled and interrupt-driven process activation. We consider the effect of combinations of these process activation styles on a static, priority-based, preemptive scheduler. Given a set of periodic tasks and a set of resources (e.g. processors), a configuration is defined as: i) a mapping of each process to a resource; ii) assignment of priority to each process; and iii) a mapping of each interprocess communication event to either a polled or interrupt-driven implementation. We present a new method which utilizes an exact schedule analysis to determine a configuration which can meet hard real time deadlines subject to a fixed limit on the number of interrupts available per resource. Task graph examples and comparisons are used to validate the method.