Evaluation of Computing in Memory Architectures for Digital Image Processing Applications

Authors:
Affiliations:
Venue:
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Year:
1999

Citing 0
Cited 3

SAGE: an automatic analyzing system for a new high-performance SoC architecture-processor-in-memory

Journal of Systems Architecture: the EUROMICRO Journal
Critical Block Scheduling: A Thread-Level Parallelizing Mechanism for a Heterogeneous Chip Multiprocessor Architecture

Languages and Compilers for Parallel Computing
Toward to utilize the heterogeneous multiple processors of the chip multiprocessor architecture

EUC'07 Proceedings of the 2007 international conference on Embedded and ubiquitous computing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these architectures can be custom tailored to the demands of real-time image processing. This paper identifies and describes candidate computing in memory architectures, and evaluates their performance on several image-processing algorithms.