Area, Performance, and Yield Implications of Redundancy in On-Chip Caches

Authors:
Brian Anthony
Affiliations:
-
Venue:
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Year:
1999

Citing 0
Cited 3

DEFCAM: A design and evaluation framework for defect-tolerant cache memories

ACM Transactions on Architecture and Code Optimization (TACO)
A novel NoC-based design for fault-tolerance of last-level caches in CMPs

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
NoC-based fault-tolerant cache design in chip multiprocessors

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

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Abstract

Recent advances in system design are presented. The shift towards flexible hardware architectures that can support a variety of applications via programmability and reconfigurability is underlined. Essential to this process is the definition and use ...