Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Timing Analysis with Implicitly Specified False Paths
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
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Finding the longest path and the worst delay is the most important task in static timing analysis. However, in almost every digital circuit, there exists false paths, which are logically impossible, or designers do not care about their delays. This paper presents a new method to calculate the worst delay of a circuit with known false paths. It every node with marks false path information. When searching for the longest path, it stores delays on nodes conditionally with false paths matched up to the node, thus reduces the number of cache entries and eliminates revisits. This method can be applied to incremental delay calculation with little change. Experiments show that the new method significantly better than path enumeration without conditional cache.