Low Power Video Object Motion-Tracking Architecture for Very Low Bit Rate Online Video Applications

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Venue:
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

Citing 4
Cited 0

Discrete-time signal processing

Discrete-time signal processing
Digital Image Warping

Digital Image Warping
Low Power VLSI Architecture for 2D-Mesh Video Object Motion Tracking

WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
On minimizing hierarchical mesh coding overhead: (HASM) hierarchical adaptive structured mesh approach

ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 04

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Abstract

This paper presents low power VLSI architecture for video object motion tracking that can be used in very low bit rate online video applications. Power has been reduced at both algorithmic and arithmetic levels. The video object motion-tracking architecture consists of two main parts, a mesh-based motion estimation unit and a mesh-based motion compensation unit. The mesh-based motion estimation unit implements parallel block matching motion estimation units to optimize the latency. The mesh-based motion compensation unit uses parallel multiplication-free affine core. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications.