Reconfigurable Systems: New Activities in Asia
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Reconfigurable Hardware SAT Solvers: A Survey of Systems
IEEE Transactions on Computers
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An architecture is proposed for a forward checking tree search which is used for solving satisfiability problems. In this design, the FPGA on-chip RAM feature is used to achieve a large improvement in density over a straight forward implementation using configurable logic blocks, enabling much larger problems to be solved. In addition, the boolean function to be satisfied is runtime configurable. A prototype implementation of the design operated success-fully at 10MHz for a 50 variable, 80 clause 3-SAT problem.