Model Reuse through Hardware Design Patterns
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A FFT/IFFT soft IP generator for OFDM communication system
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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Intellectual Property (IP) reuse approaches are known as the better way to bridge the gap between performance and time-to-market for the design of entire systems on a single chip (SoC). Despite standardization efforts and recent advances in design reuse methodology, a lot of challenges have to be addressed to make design-reuse methodology come-of-age. It is now accepted that a SoC will be synthesized from a high-level functional description using a common language. Specifying the IP at the behavioral level appears as the most promising solution to achieve a real efficiency of design reuse. In this paper we propose a methodology to specify and use Behavioral Level IP (BL-IP). Thus, IP designer tasks are easier due to the unified representation offered by this level of abstraction. The genericity of a behavioral IP permits efficient optimizations and make application context adaptations a reality. We propose a unified framework to define an IP at the behavioral level and to tune a particular block according to designer needs. Therefore, we define the IP generator tool and the Universal High Level Synthesis concept.