An implementation of capabilities on the PDP-11/45

Authors:
Charles Hoch;J. C. Browne
Affiliations:
The University of Texas, Austin, Texas;The University of Texas, Austin, Texas
Venue:
ACM SIGOPS Operating Systems Review
Year:
1980

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Abstract

This paper defines a capability implementation which uses the memory management hardware and the TRAP instruction of the higher members of the Digital Equipment Corporation PDP-11/XX (XX = 34, 45, 55, 70) to create a capability architecture processor. No modifications to hardware are necessary. The architecture created has a strong similarity to that of the Plessey 250. An operating system based on this architecture could provide a basis for implementation of highly reliable and secure software systems on a common and inexpensive minicomputer.