Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
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IEEE/ACM Transactions on Networking (TON)
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
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Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
ACM Transactions on Computer Systems (TOCS)
IEEE/ACM Transactions on Networking (TON)
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IEEE/ACM Transactions on Networking (TON)
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This work considers the use of an SMT (simultaneous multithreading) processor in lieu of the conventional processor(s) in a router and evaluates quantitatively the potential gains as a result. An SMT processor exploits the benefits of both ILP (instruction level parallelism) and TLP (thread-level parallelism), suitable for the next generation routers, in which an increased number of functions are to be implemented. The use of an SMT processor not only allows router functions to be decomposed into multiple threads but also designates separate threads to handle different incoming traffic streams of a router to exploit TLP, potentially attaining performance improvement. Additionally, an SMT processor may admit new router functions or added traffic streams relatively easily without compromising much existing performance levels, via including a new thread (or threads) to perform one newly added function or traffic stream. This router design appears to have better flexibility and adaptability. In order to assess the benefits of this design approach, we implemented three key router functions (i.e., packet header extraction, packet header manipulation, and longest-prefix matching) as threads using an SMT simulator (SMTSIM) for performance evaluation. The results of this router design approach are collected and compared with those of conventional routers.