A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
| Hi-index | 0.00 |
High-speed interconnects have been gaining much attention from the computer industry recently as interconnects are becoming a limiting factor to the performance of modern computer systems. This trend will even continue in the near future as technology improves. In this paper, we consider efficiently routing permutations in a class of switch-based interconnects. Permutation is an important communication pattern in parallel and distributed computing systems. We present a generic approach to realizing arbitrary permutations in a class of unique-path, self-routable multistage networks, such as baseline, omega, and banyan networks. It is well-known that this type of interconnect has low hardware cost but can realize only a small portion of all possible permutations between its inputs and outputs in a single pass. In this paper, we consider routing arbitrary permutations with link-disjoint paths and node-disjoint paths in such interconnects in a minimum number of passes. In particular, routing with node-disjoint paths has important applications in the emerging optical interconnects. We employ and further expand the Latin square technique used in the all-to-all personalized exchange algorithms for this class of multistage networks [1] for general permutation routing. As can be seen, our implementation of permutation routing is optimal in terms of the number of passes that messages are transmitted through the network, and it is near-optimal in network transmission time for sufficiently long messages.