Networking support for large scale multiprocessor servers
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
IEEE/ACM Transactions on Networking (TON)
Cache behavior of network protocols
SIGMETRICS '97 Proceedings of the 1997 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Performance modeling of multiprocessor implementations of protocols
IEEE/ACM Transactions on Networking (TON)
Evaluating and Optimizing Thread Pool Strategies for Real-Time CORBA
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Applying a pattern language to develop application-level gateways
Design patterns in communications software
Flexible Control of Parallelism in a Multiprocessor PC Router
Proceedings of the General Track: 2002 USENIX Annual Technical Conference
The effectiveness of affinity-based scheduling in multiprocessor networking
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
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Message-based process architectures are widely regarded as an effective method for structuring parallel protocol processing on shared memory multi-processor platforms. A message-based process architecture binds one or more processing elements with data messages and control messages received from applications and network interfaces. In this architecture, parallelism is achieved by simultaneously escorting multiple messages on separate processing elements through a stack of protocol tasks. The paper reports performance results from empirical comparisons of a connection-oriented TCP/IP protocol stack implemented using two different parallel message-based process architectures. These performance experiments measure the throughput, context switching, and synchronization exhibited by the two process architectures on a shared memory multi-processor platform. The experimental results demonstrate the extent to which the selection of a parallel process architecture affects protocol stack performance.