Reversible circuit synthesis of symmetric functions using a simple regular structure
RC'13 Proceedings of the 5th international conference on Reversible Computation
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This paper focuses on the fixed polarity Reed-Muller (FPRM) expression of multiple-valued logic (MVL) symmetric functions. In the FPRM expression, each variable occurs in exactly one complemented form. We show properties of the FPRM of partially symmetric functions and report experimental results for certain benchmark functions.