Hierarchical 3D-Torus Interconnection Network

Authors:
S. Horiguchi;T. Ooki
Affiliations:
-;-
Venue:
ISPAN '00 Proceedings of the 2000 International Symposium on Parallel Architectures, Algorithms and Networks
Year:
2000

Citing 0
Cited 2

A deadlock-free routing algorithm using minimum number of virtual channels and application mappings for Hierarchical Torus Network

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Research on next-generation scalable routers implemented with H-Torus topology

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Abstract

Three dimensional (So) stacked implementation has been proposed as a new technology for massively parallel computers. However, two major limitations have hindered the progress in this direction: the technology of vertical interconnects and the cost in terms of area for these vertical interconnects. Each vertical interconnect requires 300,um x 300µm area,thus liberal is prohibited. Clearly, an interconnection philosophy which minimizes these vertical links can contribute to the success of a 30 implementation. Hierarchical 3D-Torusnetwork, called H3D-torus has been proposed to reduce the number of vertical links in 3D stackedimplementation but keeping good network feature. This paper addresses the architectural details of HSD-torus network, and explores aspects such as the network diameter, the peak number of vertical links, and VLSI layout area for the HQD-torus network as well as forseveral commonly used networks for parallel computers.