Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control

Authors:
Takayasu Sakurai
Affiliations:
-
Venue:
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Year:
2000

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Abstract

Lowering operating voltage, VDD, is a key to low-power CMOS digital VLSI's. In order to complete a certain task in a required time and in order to keep leakage current within a tolerable level in the low VDD designs, VDD and VTH control is obligatory. This talk will cover several of the schemes including multi-VTH, variable VTH, multi-VDD and variable VDD to achieve low-power systems. Circuit level ideas to software related research is described.