Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Supply voltage scalable system design for low poweris investigated using self-timed circuits in this paper. Twoarchitectures are proposed to achieve supply voltagescalability, for preserved quality and energy-qualitytradeoff respectively, In the fist architecture, the supply-voltageautomatically tracks the input data rate of thedata path so that the supply-voltage can be kept as smallas possible while maintaining the speed requirement andprocessing quality. In the second one, further energysaving is achieved at the cost of signal-noise-ratio loss indigital signal processing when an ultra-low supplyvoltage is applied. Cadence simulation shows theeffectiveness for both architectures. More than 40% to70% power can be saved by introducing -15dB to -10 dBerror in a case study: speech signal processing.