A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes
Journal of VLSI Signal Processing Systems
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This paper presents a model for estimating the rain current in deep submicron CMOS devices. The model presented is an extension of Sakurai and Newton's model (SN-model)[1,2 ],and hence is referred to as the modi ?ed SN-model (MSN-model). The proposed model preserves the simplicity of the SN-model while providing accurate drain current estimates for varying device widths. The transistor drain current values predicted by the proposed model are compared with HSPICE level 49 simulations for 0.25 µm and 0.18 µm CMOS processes. Manually computed current values for inverter circuits via the proposed model match HSPICE simulations on average to within 1.2%(3% maximum)over a wide range of transistor widths, fanouts, and input rise/fall times. Further, this model is accurate in estimating the current in series-connected transistors having arbitrary widths, where the previous SN-model requires a delay degradation factor with transistors of equal sizes in order to work [3 ]. The proposed model has been successfully incorporated into a senior level circuit design course at the University of Illinois at Urbana-Champaign.