Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
ACM Transactions on Embedded Computing Systems (TECS)
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The increasing size and complexity of embedded software requires extremely fast instruction-set simulation. Compiled instruction-set simulation can provide high simulation speed, but the cost of generating and compiling the simulator can be a problem. We claim that efficient compiled instruction-set simulation with small startup costs is possible, using our assembler-level approach. We present Absciss, a retargetable and flexible system that generates optimized compiled simulators from assembler programs. Experimental results show the produced simulators to be significantly faster than interpretive simulators, and also show that our assembler-based approach allows to master the simulator generation and compilation times.