A virtual memory management scheme for simulation environment

  • Authors:

  • S. Mittra

  • Affiliations:

  • -

  • Venue:
  • IVC '95 Proceedings of the 4th IEEE International Verilog HDL Conference
  • Year:
  • 1995

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Abstract

A virtual memory management scheme is proposed for integrating large memory in the simulation environment. This is a novel extension to the Verilog-XL simulator from Cadence Design Systems. The scheme provides a user-transparent mechanism to instantiate a large chunk of memory without being limited by the main-memory of the simulating machine.