The impact of address allocation and routing on the structure and implementation of routing tables

  • Authors:
  • Harsha Narayan;Ramesh Govindan;George Varghese

  • Affiliations:
  • University of California, San Diego, La Jolla, CA;University of Southern California, La Jolla, CA;University of California, San Diego, La Jolla, CA

  • Venue:
  • Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
  • Year:
  • 2003

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Abstract

The recent growth in the size of the routing table has led to an interest in quantitatively understanding both the causes (eg multihoming) as well as the effects (eg impact on router lookup implementations) of such routing table growth. In this paper, we describe a new model called ARAM that defines the structure of routing tables of any given size. Unlike simpler empirical models that work backwards from effects (eg current prefix length distributions), ARAM approximately models the causes of table growth (allocation by registries, assignment by ISPs, multihoming and load balancing). We show that ARAM models with high fidelity three abstract measures (prefix distribution, prefix depth, and number of nodes in the tree) of the shape of the prefix tree --- as validated against 20 snapshots of backbone routing tables from 1997 to the present. We then use ARAM for evaluating the scalability of IP lookup schemes, and studying the effects of multihoming and load balancing on their scaling behavior. Our results indicate that algorithmic solutions based on multibit tries will provide more prefixes per chip than TCAMs (as table sizes scale toward a million) unless TCAMs can be engineered to use 8 transistors per cell. By contrast, many of today's SRAM-based TCAMs use 14-16 transistors per cell.