The grid block device: performance in LAN and WAN environments
EGC'05 Proceedings of the 2005 European conference on Advances in Grid Computing
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We present design details and some initial performance results of a novel scalable shared memory multiprocessor architecture that incorporates the major strengths of several contemporary multiprocessor architectures while avoiding their most serious weaknesses. Specifically, our architecture design incorporates the automatic data migration and replication features of cache-only memory architecture (COMA) machines, but replaces much of the complex hardware of COMA with a software layer that manages page-grained cache space allocation, as found in distributed virtual shared memory (DVSM) systems. Unlike DVSM however, pages are sub-divided into cache-line sized blocks, and for shared pages the coherence of these blocks is maintained by hardware. Moving much of COMA''s hardware functionality to software simplifies the machine design and reduces development time, while supporting fine-grain coherence in hardware greatly decreases the impact of DVSM software overheads. We call the resulting hybrid hardware and software multiprocessor architecture Simple COMA. By allowing shared data to be replicated in a node''s main memory (in addition to its caches), the number of remote memory accesses is greatly reduced compared to a traditional cache coherent non-uniform memory access (CC-NUMA) architecture. Preliminary results indicate that despite the reduced hardware complexity and the need to handle allocation page faults in software, the performance of Simple COMA is comparable to that of more complex all-hardware designs.