Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays
IEEE Transactions on Parallel and Distributed Systems
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Advances in VLSI (Very Large Scale Integration) allow increasingly larger and more complex systems to be fabricated on a single chip or wafer. As the number of elements in these systems increases, the problem of tolerating faulty elements becomes more and more important. This thesis addresses reconfiguration problems for several important fault tolerant architectures. We show that for some fault tolerant architectures the corresponding reconfiguration problems can be solved in polynomial time while for other related architectures reconfiguration is NP-hard. For those reconfiguration problems that can be solved in polynomial time, we present fast (and in many cases asymptotically optimal) algorithms. For the NP-hard reconfiguration problems, we propose several strategies. For some problems, polynomial time approximation algorithms are presented that yield provably good, but not necessarily optimal, solutions. For some reconfiguration problems, however, approximation algorithms are not meaningful. For these problems effective search strategies and heuristics are proposed.