An abstract machine for restricted AND-parallel execution of logic programs
Proceedings on Third international conference on logic programming
HPS, a new microarchitecture: rationale and introduction
MICRO 18 Proceedings of the 18th annual workshop on Microprogramming
Studies in Prolog architectures
Studies in Prolog architectures
A distributed prolog system with AND-parallelism
Proceedings of the Twenty-First Annual Hawaii International Conference on Software Track
A High Performance Architecture for PROLOG
A High Performance Architecture for PROLOG
The Berkeley PLM Instruction Set: An Instruction Set for Prolog
The Berkeley PLM Instruction Set: An Instruction Set for Prolog
The and/or process model for parallel interpretation of logic programs
The and/or process model for parallel interpretation of logic programs
A parallel execution model for prolog
A parallel execution model for prolog
Parallel unification scheduling in prolog
Parallel unification scheduling in prolog
The 16-fold way: a microparallel taxonomy
MICRO 26 Proceedings of the 26th annual international symposium on Microarchitecture
| Hi-index | 0.00 |
We describe the Parallel Unification Machine (PLUM), a Prolog processor that exploits fine grain parallelism using multiple function units executing in parallel. In most cases the execution of bookkeeping instructions is almost completely overlapped by unification, and the performance of the processor is limited only by the available unification parallelism. We present measurements from a register transfer level simulator of PLUM. These results show that PLUM with 3 Unification Units achieves an average speedup of approximately 3.4 over the Berkeley VLSI-PLM, which is usually regarded as the current highest performance special purpose, pipelined Prolog processor. Measurements that show the effects of multiple Unification Units and memory access time on performance are also presented.