An Interconnect-Aware Methodology for Analog and Mixed Signal Design, Based on High Bandwidth (Over 40 Ghz) On-Chip Transmission Line Approach

  • Authors:
  • D. Goren;M. Zelikson;T. Galambos;R. Gordin;B. Livshitz;A. Amir;A. Sherman;I. Wagner

  • Affiliations:
  • IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel;IBM Haifa Research and Development Labs, MATAM, Haifa 31905, Israel

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2002

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Abstract

This paper presents an on-chip, interconnect-awaremethodology for high-speed analog and mixed signal(AMS) design which enables early incorporation of on-chiptransmission line (T-line) components into AMS design flow.The proposed solution is based on a set of parameterizedT-line structures, which include single and two coupled microstriplines with optional side shielding, accompanied bycompact true transient models. The models account for frequencydependent skin and proximity effects, while maintainingpassivity requirements due to their pure RLC nature.The signal bandwidth supported by the models coversa range from DC to 100 GHz. The models are currentlyverified in terms of S-parameter data against hardware (upto 40 GHz) and against EM solver (up to 100 GHz). Thismethodology has already been used for several designs implementedin SiGe (Silicon-Germanium) BiCMOS technology.