Clock schedule verification with crosstalk
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Timing Verification with Crosstalk for Transparently Latched Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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This paper addresses verifying the timing of circuits containinglevel-sensitive latches in the presence of cross talk.We show that three consecutive periodic occurrences of theaggressor's input switching window must be compared withthe victim's input switching window. We propose a newphase shift operator to allow aligning the aggressor's threerelevant switching windows with the victim's input signals.We solve the problem iteratively in polynomial time, andshow an upper bound on the number of iterations equal tothe number of capacitors in the circuit. Our experimentsdemonstrate that eliminating false coupling results in findinga smaller clock period at which a circuit will run.