Architecture, design, and operating characteristics of a 12-ns CMOS functional cache chip

Authors:
R. Matick;R. Mao;S. Ray
Affiliations:
-;-;-
Venue:
IBM Journal of Research and Development
Year:
1989

Citing 1
Cited 2

Functional cache chip for improved system performance

IBM Journal of Research and Development

An integrated memory management scheme for dynamic alias resolution

Proceedings of the 1991 ACM/IEEE conference on Supercomputing
Logic-based eDRAM: origins and rationale for use

IBM Journal of Research and Development - Electrochemical technology in microelectronics

Quantified Score

Hi-index	0.00

Visualization

Abstract