Quantifying the Impact of Architectural Scaling on Communication

Authors:
Taliver Heath;Samian Kaur;Richard P. Martin;Thu D. Nguyen
Affiliations:
-;-;-;-
Venue:
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Year:
2001

Citing 0
Cited 1

Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services

HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture

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Abstract

Abstract: As processor performance increases, there is a corresponding increase in the demands on the memory system, including caches. Research papers have proposed partitioning the cache into instruction/data, temporal/non-temporal, and/or stack/non-stack ...