An Analytical Model for Trace Cache Instruction Fetch Performance

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ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Year:
2001

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Resource sharing in performance models

EPEW'07 Proceedings of the 4th European performance engineering conference on Formal methods and stochastic models for performance evaluation

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Abstract

Abstract: This paper presents an analytical model of instruction fetch performance of a Trace Cache. This paper also presents an analytical model of miss rate of a Trace Cache. These models can be used to analyze performance and behavior of a Microarchitecture of a processor. These models are implemented in a new Microarchitecture tool Tulip. Performances of several benchmark programs based on Tulip are also presented in this paper.