On communication latency in PRAM computations
SPAA '89 Proceedings of the first annual ACM symposium on Parallel algorithms and architectures
A bridging model for parallel computation
Communications of the ACM
LogP: towards a realistic model of parallel computation
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Technology advances in the Intel Paragon system
SPAA '93 Proceedings of the fifth annual ACM symposium on Parallel algorithms and architectures
Towards efficiency and portability: programming with the BSP model
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
A quantitative comparison of parallel computation models
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
BSPlib: The BSP programming library
Parallel Computing
IEEE Transactions on Parallel and Distributed Systems
A quantitative comparison of parallel computation models
ACM Transactions on Computer Systems (TOCS)
Toward Optimal Complete Exchange on Wormhole-Routed Tori
IEEE Transactions on Computers
The Paderborn University BSP (PUB) library
Parallel Computing
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Experimental data validating some of the proposed parallel computation models on the Intel Paragon is presented. This architecture is characterized by a large bandwidth and a relatively large startup cost of a message transmission, which makes it extremely important to employ bulk transfers. The models considered are the BSP model, in which it is assumed that all messages have a fixed short size, and the BPRAM, in which block transfers are rewarded.