PYRROS: static task scheduling and code generation for message passing multiprocessors
ICS '92 Proceedings of the 6th international conference on Supercomputing
Models of machines and computation for mapping in multicomputers
ACM Computing Surveys (CSUR)
ANDES: evaluating mapping strategies with synthetic programs
Journal of Systems Architecture: the EUROMICRO Journal
Divide-and-conquer mapping of parallel programs onto hypercube computers
Journal of Systems Architecture: the EUROMICRO Journal - Special double issue: massively parallel computing systems
Performance Comparison of Strategies for Static Mapping of Parallel Programs
HPCN Europe '97 Proceedings of the International Conference and Exhibition on High-Performance Computing and Networking
IEEE Transactions on Computers
A New Model for Static Mapping of Parallel Applications with Task and Data Parallelism
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Exploiting Knowledge of Temporal Behaviour in Parallel Programs for Improving Distributed Mapping
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Proceedings of the 8th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Partial task assignment of task graphs under heterogeneous resource constraints
Proceedings of the 40th annual Design Automation Conference
Visual programming support for graph-oriented parallel-distributed processing: Research Articles
Software—Practice & Experience
A New Task Graph Model for Mapping Message Passing Applications
IEEE Transactions on Parallel and Distributed Systems
Modelling message-passing programs for static mapping
EURO-PDP'00 Proceedings of the 8th Euromicro conference on Parallel and distributed processing
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A fundamental issue affecting the performance of a parallel program is the assignment of tasks to processors in order to get the minimum completion time. In this paper, we present a compilation-time two-stage mapping strategy (denoted as CREMA) used for mapping arbitrary programs (modeled as TIG graphs) onto message-passing parallel systems with any architecture. In contrast to most of the other approaches found in the literature, CREMA is not tied to any particular architecture or any specific algorithm. The first stage is based on task clustering and task reassignment algorithms that contract the original task graph. The second stage takes the contracted graph and tries to successfully match the physical properties of the target system. It has been evaluated for a wide range of both regular and irregular graphs that correspond to some well-known real applications. The results show that CREMA provides a good trade-off between mapping quality and computational complexity.