Hardware support for fine-grained event-driven computation in Anton 2
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
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Our new architecture, known as Scheduled DataFlow(SDF) system deviates from current trend of buildingcomplex hardware to exploit Instruction LevelParallelism (ILP) by exploring a simpler, yetpowerful execution paradigm that is based ondataflow, multithreading and decoupling of memoryaccesses from execution. A program is partitionedinto non-blocking threads. In addition, all memoryaccesses are decoupled from the thread's execution.Data is pre-loaded into the thread's context(registers), and all results are post-stored after thecompletion of the thread's execution. Even thoughmultithreading and decoupling are possible withcontrol-flow architecture, the non-blocking andfunctional nature of the SDF system make it easier tocoordinate the memory accesses and execution of athread. In this paper we show some recentimprovements on SDF implementation, wherebythreads exchange data directly in register contexts,thus eliminating the need for creating thread frames.Thus it is now possible to explore the scalability ofour architecture's performance when more registercontexts are included on the chip.