Z4: a new depth-size optimal parallel prefix circuit with small depth
Neural, Parallel & Scientific Computations
Constructing zero-deficiency parallel prefix adder of minimum depth
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Prefix computation has many applications, and should be implemented as a primitive operation. Many combinational circuits for performing the prefix operation in parallel, called parallel prefix circuits, have been designed and studied. The size of a prefix circuit D, s(D), is the number of operation nodes in D, and the depth of D, d(D), is the maximum level of operation nodes in D. Smaller depth implies faster computation, while smaller size implies less power consumption and smaller area in VLSI implementation and thus less cost. D is depth-size optimal if d(D) + s(D) = 2n - 2. Another circuit parameter is fan-out. A circuit having a smaller fan-out is faster and smaller in VLSI implementation. Thus, a circuit should have a small fan-out for it to be of practical use. In this paper, we take a new approach to designing a depth-size optimal parallel prefix circuit, WE4, with fan-out 4 and small depth. In many cases of n, WE4 has the smallest depth among all known prefix circuits.