Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Hardware architectures for public key cryptography
Integration, the VLSI Journal
Efficient scalable VLSI architecture for Montgomery inversion in GF(p)
Integration, the VLSI Journal
Subtraction-free almost montgomery inverse algorithm
Information Processing Letters
Improvement to Montgomery Modular Inverse Algorithm
IEEE Transactions on Computers
An RNS implementation of an Fpelliptic curve point multiplier
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Subtraction-free Almost Montgomery Inverse algorithm
Information Processing Letters
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Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montgomery modular inverse operation. The implementations are based on the same inversion algorithm, however, one is fixed (fully parallel) and the other is scalable. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate within better or similar speed. Both hardware designs are compared based on their speed and area. The area of the scalable design is on average 42% smaller than the fixed one. The delay of the designs, however, depends on the actual data size and the maximum numbers the hardware can handle. As the actual data size approach the hardware limit the scalable hardware speedup reduces in comparison to the fixed one, but still its delay is practical.